An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, capacitors, and resistors. Commonly known as a “chip” or a “package”, an integrated circuit is generally encased in hard plastic, forming a “package”. The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement. Often, many such packages are electrically coupled so that the chips therein form an electronic circuit to perform certain functions.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A layout includes shapes that the designer selects and positions to achieve a design objective. The objective is to have the shape—the target shape—appear on the wafer as designed. However, the shapes may not appear exactly as designed when manufactured on the wafer through photolithography. For example, a rectangular shape with sharp corners may appear as a rectangular shape with rounded corners on the wafer.
Once a design layout, also referred to simply as a layout, has been finalized for an IC, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacture, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components of the IC. This process is known as photolithography.
A manufacturing mask is a mask usable for successfully manufacturing or printing the contents of the mask onto wafer. During the photolithographic printing process, radiation is focused through the mask and at certain desired intensity of the radiation. This intensity of the radiation is commonly referred to as “dose”. The focus and the dosing of the radiation has to be precisely controlled to achieve the desired shape and electrical characteristics on the wafer.
An IC may use many layers of silicon to implement a circuit. In other words, components forming the circuit may be placed on different layers of silicon in a chip. Interconnects connecting the components on one layer to components on different layers go through the silicon layer. Such interconnects are also known as through silicon vias (TSVs).
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A Field Effect Transistor (FET) is a semiconductor device that has controls the electrical conductivity between a source of electric current (source) and a destination of the electrical current (drain). The FET uses a semiconductor structure called a “gate” to create an electric field, which controls the shape and consequently the electrical conductivity of a channel between the source and the drain. The channel is a charge carrier pathway constructed using a semiconductor material.
Many semiconductor devices are planar, i.e., where the semiconductor structures are fabricated on one plane. A non-planar device is a three-dimensional (3D) device where some of the structures are formed above or below a given plane of fabrication.
A fin-Field Effect Transistor (finFET) is a non-planar device in which a source and a drain are connected using a fin-shaped conducting channel (fin) above the insulator layer. In an FET, a gate has a source-side and a drain-side. Generally, a finFET is fabricated as a multi-gate device in which two or more gates are coupled using one or more fin structures by connecting a drain of one gate to the source of another gate using a fin. For example, a fin of a finFET is usually fabricated between two gates such that the source of one gate is on one side of the fin and the drain of the other gate is on an opposite side of the fin. The direction along the lateral length of the fin running from one gate to the other gate is referred to herein as a lateral running direction of the fin.
A CB contact is an electrical connection that connects two gates. A CB contact is fabricated on one surface—usually the top surface (also referred to herein as the frontside) of the device. A circuit external to the finFET uses the CB contact to electrically connect a part of the circuit to a gate in the finFET. The frontside of the finFET is the side opposite to the side of the gate facing the substrate of the device. The side of the gate facing the substrate is referred to herein as the backside of the device.
A TS contact is an electrical contact that provides electrical connectivity to the one or more fins that connect two or more gates to one another. Presently, the TS contact is also fabricated on the same surface as the CB contact, although electrically insulated from the CB contact. A circuit external to the finFET uses the TS contact to electrically connect a part of the circuit to a fin in the finFET.
The illustrative embodiments recognize that the present methods and techniques for fabricating a finFET suffer from several problems. For example, placing the CB contact and the TS contact on the same surface causes the only separation between the two contacts to be the fabricated distance between them. Given that these devices are extremely small—of the order of a few nanometers, presently manufactured using 14 nanometer (nm) technology—creates a risk of short circuit between these contacts. Furthermore, the insulation separating two conducting contacts on the same surface also creates an unintended capacitor, which gives rise to undesirable—parasitic—capacitance in the finFET device.
The illustrative embodiments further recognize that fabricating a finFET contact in places other than the surface where they are presently located is difficult given the non-planar geometry of the finFET device. Therefore, a method for fabricating the CB and TS contacts on different surfaces of a finFET would be useful.